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contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate (board or glass) or product design stage. 2. always test and inspect products under the environme nt with no penetration of light. s 6b 07 59 81 com / 128 seg driver & controller for stn lcd march 2001 ver. 2.1
81 com / 128 seg dri ver & controller for stn lcd preli minary spec. ver. 2. 0 s6b0759 2 s6b0759 specification revision history version content date 0.0 original july.1999 0.1 remove hpmb,cs2 pin and change vol, voh value july.199 9 0.2 modify pad dimensions and chip configuration aug. 1999 0.3 modify serial/parallel timing requirements ;added icon enable/disable function dec. 1999 1.0 jan. 2000 1.1 modify 6800 parallel interface timing feb 2000 1.2 add the programming guide - lines comment for n - line inversion mar 2000 1.3 modify dynamic current consumption value(idd2) and sleep mode current value(idds1) june 2000 2.0 modify temperature coefficient( - 0.05% to ? 0.075%) aug 2000 2.1 added detail information for several items ma r.2001
s6b0759 prel iminary spec. ver. 2.0 81 com / 128 seg driver & controller for st n lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 block diagram ................................ ................................ ................................ ................................ .......... 3 pad configuration ................................ ................................ ................................ ................................ .. 4 pin description ................................ ................................ ................................ ................................ ...... 10 power sup ply ................................ ................................ ................................ ................................ ............ 10 lcd driver supply ................................ ................................ ................................ ................................ ...... 10 system control ................................ ................................ ................................ ................................ .......... 11 microprocessor interface ................................ ................................ ................................ ............................ 12 lcd driver outputs ................................ ................................ ................................ ................................ ..... 14 functional description ................................ ................................ ................................ ....................... 15 microprocessor interface ................................ ................................ ................................ ............................ 15 display data ram (ddram) ................................ ................................ ................................ ................. 20 lcd display circuits ................................ ................................ ................................ ................................ .. 24 lcd driver circuit ................................ ................................ ................................ ................................ ...... 26 power supply circuits ................................ ................................ ................................ ................................ . 28 referece circuit examples ................................ ................................ ................................ ................ 33 reset circuit ................................ ................................ ................................ ................................ ............. 35 instruction description ................................ ................................ ................................ ..................... 36 specifications ................................ ................................ ................................ ................................ ........ 57 absolute maximum ratings ................................ ................................ ................................ ........................ 57 dc characteristics ................................ ................................ ................................ ................................ ..... 58 ac characteristics ................................ ................................ ................................ ................................ ..... 61 reference applications ................................ ................................ ................................ ...................... 65 microprocessor i nterface ................................ ................................ ................................ ............................ 65 connections between s6b0759 and lcd panel ................................ ................................ .......................... 67
s6b0759 81 com/128 seg driver & control ler for stn lcd 2 introduction the s6b0759 is a driver and controller lsi for graphic dot - matrix liquid crystal display systems. it contains 81 commo n and 128 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8 - bit parallel display data and stores in an on - chip display data ram of 81 128 bits. it provides a highly flexible display section due to 1 - to - 1 co rrespondence between on - chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no externally operating clock to minimize power consumption. in addition, because it contains power supply circuits necessar y to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits ? 81 common outputs, 128 segment outputs applicable duty ratios programmable duty ratio applicable lcd bias maximum display area 1/17 to 1/81 1/4 to 1/11 81 128 ? various partial display ? partial window moving and data scrolling on - chip display data ram ? capacity: 81 128 = 10,368 bits ? bit data "1": a dot of display is illuminated. ? bit data "0": a dot of display is not illuminated. microprocessor interface ? 8 - bit parallel bi - directional interface with 6800 - series or 8080 - series. ? spi (serial peripheral interface) available. (only write operation) on - chip low power analog circuit ? on - chip oscillator circuit ? voltage c onverter ( 3, 4, 5 or 6) ? voltage regulator (temperature coefficient: - 0.075%/ c or external input) ? on - chip electronic contrast control function (64 steps) ? voltage follower (lcd bias: 1/4 to 1/11) operating voltage range ? supply voltage (v dd ): 1.8 to 3.3 v ? lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 15.0 v low power consumption ? tbd m a typ. (internal power supply on and display off) package type ? gold bumped chip or tcp
81 com/128 seg drive r & controller for s tn lcd s6b0759 3 block diagram column address circuit page address circuit display data ram 81x128=10,368 bits line address circuit bus holder status register instruction decoder & register mpu interface (parallel & serial) display timing generator circuit/ oscillstor v/f circuit 128 segment driver circuit db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) rw_wr e_rd rs com1 com0 seg127 seg126 : seg1 seg0 v/c circuit v0 v1 v2 v3 v4 v dd v ss 2 v0 vr intrs vout c1- c1+ c2- c2+ c3+ 82 common driver circuit com79 coms seg2 seg125 : segment controller common controller resetb ps1 ps0 cs1b ref vext v/r circuit c4+ c5+ internal power supply : : vss2 vss1 vci figure 1 . block diagram
s6b0759 81 com/128 seg driver & control ler for stn lcd 4 pad configuration y 155 312 154 313 124 343 123 1 (0,0) x dummy pad normal pad s6b0759 (top view , pad up) figure 2 . s6b0759 chip configuration table 1. s6b0759 pad dimension item pad no. size unit x y chip size ? 9980 2380 um pad pitch input 1 to 123 70 outp ut 125 to 152 60 157 to 310 315 to 342 nc 124,343 70 154,155,312,313 80 153,156,311,314 70/80 bumped pad size(max.) 1 to 123 50 100 124 110 60 125 to 152 110 40 153 to 154 110 60 155 to 156 60 110 157 to 310 40 110 311 to 312 60 110 313 to 314 110 60 315 to 342 110 40 343 110 60 bumped pad height all pad 14(typ.) note: dummy to dummy pad pitch is 80 um. dummy to normal pad pitch is 70 um.
81 com/128 seg drive r & controller for s tn lcd s6b0759 5 cog align key coordinate ilb align key coordinate(with gold bump*) 30 m m 30 m m (+4265 , +465) 30 m m 30 m m 30 m m 30 m m (-4265 , -375) 30 m m 30 m m 30 m m 42 m m 108 m m 108 m m 42 m m (+4310 , -510) 108 m m 42 m m x x (-4310 , +510) x x 42 m m 108 m m 30 m m 30 m m 30 m m * when designing electrode pattern must be prohibited on this area (ilb align key). if electrode pattern is used for routing over this area, it can be happened pattern - short t hrough bumped pattern on ilb align key.
s6b0759 81 com/128 seg driver & control ler for stn lcd 6 pad center coordinat es table 2. pad center coordinates [unit : m m] pad pad coordinate pad pad coordinate pad pad coordinate no. name x y no. name x y no. name x y 1 test1 - 4270 - 1075 34 vdd - 1960 - 1075 67 c3 + 350 - 1075 2 test2 - 4200 - 1075 35 vdd - 1890 - 1075 68 c3+ 420 - 1075 3 test3 - 4130 - 1075 36 vci - 1820 - 1075 69 c3+ 490 - 1075 4 test4 - 4060 - 1075 37 vci - 1750 - 1075 70 c1 - 560 - 1075 5 vss - 3990 - 1075 38 vci - 1680 - 1075 71 c1 - 630 - 1075 6 vdd - 3920 - 1075 39 vci - 1610 - 1075 72 c1 - 700 - 1075 7 vdd - 3850 - 1075 40 vci - 1540 - 1075 73 c1 - 770 - 1075 8 ps0 - 3780 - 1075 41 vci - 1470 - 1075 74 c1 - 840 - 1075 9 vss - 3710 - 1075 42 vci - 1400 - 1075 75 c1 - 910 - 1075 10 vdd - 3640 - 1075 43 vci - 1330 - 1075 76 c1+ 980 - 107 5 11 ps1 - 3570 - 1075 44 vss1 - 1260 - 1075 77 c1+ 1050 - 1075 12 vss - 3500 - 1075 45 vss1 - 1190 - 1075 78 c1+ 1120 - 1075 13 cs1b - 3430 - 1075 46 vss1 - 1120 - 1075 79 c1+ 1190 - 1075 14 vdd - 3360 - 1075 47 vss1 - 1050 - 1075 80 c2+ 1260 - 1075 15 vdd - 3290 - 1075 4 8 vss1 - 980 - 1075 81 c2+ 1330 - 1075 16 resetb - 3220 - 1075 49 vss2 - 910 - 1075 82 c2+ 1400 - 1075 17 rs - 3150 - 1075 50 vss2 - 840 - 1075 83 c2+ 1470 - 1075 18 vss - 3080 - 1075 51 vss2 - 770 - 1075 84 c2 - 1540 - 1075 19 rw_wr - 3010 - 1075 52 vss2 - 700 - 1075 85 c2 - 1610 - 1075 20 e_rd - 2940 - 1075 53 vss2 - 630 - 1075 86 c2 - 1680 - 1075 21 vdd - 870 - 1075 54 vout - 560 - 1075 87 c2 - 1750 - 1075 22 db0 - 2800 - 1075 55 vout - 490 - 1075 88 c2 - 1820 - 1075 23 db1 - 2730 - 1075 56 vout - 420 - 1075 89 c2 - 1890 - 1075 24 db2 - 2660 - 1 075 57 vout - 350 - 1075 90 c4+ 1960 - 1075 25 db3 - 2590 - 1075 58 vout - 280 - 1075 91 c4+ 2030 - 1075 26 db4 - 2520 - 1075 59 vout - 210 - 1075 92 c4+ 2100 - 1075 27 db5 - 2450 - 1075 60 vout - 140 - 1075 93 c4+ 2170 - 1075 28 db6 - 2380 - 1075 61 vout - 70 - 1075 94 vss 2240 - 1075 29 db7 - 231 - 1075 62 c5+ 0 - 1075 95 ref 2310 - 1075 30 vdd - 2240 - 1075 63 c5+ 70 - 1075 96 vext 2380 - 1075 31 vdd - 2170 - 1075 64 c5+ 140 - 1075 97 vdd 2450 - 1075 32 vdd - 2100 - 1075 65 c5+ 210 - 1075 98 intrs 2520 - 1075 33 vdd - 2030 - 1075 66 c3 + 280 - 1075 99 vss 2590 - 1075
81 com/128 seg drive r & controller for s tn lcd s6b0759 7 table 2. pad center coordinates (continued) [unit : m m] pad pad coordinate pad pad coordinate pad pad coordinate no. name x y no. name x y no. name x y 100 v4 2660 - 1075 135 com29 4843 - 310 170 seg0 3810 1043 101 v4 2730 - 1075 136 com28 4843 - 250 171 seg1 3750 1043 102 v4 2800 - 1075 137 com27 4843 - 190 172 seg2 3690 1043 103 v4 2870 - 1075 138 com26 4843 - 130 173 seg3 3630 1043 104 v3 2940 - 1075 139 com25 4843 - 70 174 seg4 3570 1043 105 v3 3010 - 1075 140 com24 484 3 - 10 175 seg5 3510 1043 106 v3 3080 - 1075 141 com23 4843 50 176 seg6 3450 1043 107 v3 3150 - 1075 142 com22 4843 110 177 seg7 3390 1043 108 v2 3220 - 1075 143 com21 4843 170 178 seg8 3330 1043 109 v2 3290 - 1075 144 com20 4843 230 179 seg9 3270 1043 110 v2 3360 - 1075 145 com19 4843 290 180 seg10 3210 1043 111 v2 3430 - 1075 146 com18 4843 350 181 seg11 3150 1043 112 v1 3500 - 1075 147 com17 4843 410 182 seg12 3090 1043 113 v1 3570 - 1075 148 com16 4843 470 183 seg13 3030 1043 114 v1 3640 - 1075 149 com15 4843 530 184 seg14 2970 1043 115 v1 3710 - 1075 150 com14 4843 590 185 seg15 2910 1043 116 v0 3780 - 1075 151 com13 4843 650 186 seg16 2850 1043 117 v0 3850 - 1075 152 com12 4843 710 187 seg17 2790 1043 118 v0 3920 - 1075 153 dummy 4843 780 188 seg18 2730 1043 119 v0 3990 - 1075 154 dummy 4843 860 189 seg19 2670 1043 120 vr 4060 - 1075 155 dummy 4740 1043 190 seg20 2610 1043 121 vr 4130 - 1075 156 dummy 4660 1043 191 seg21 2550 1043 122 vss 4200 - 1075 157 com11 4590 1043 192 seg22 2490 1043 123 vss 4270 - 1075 158 com10 4530 1043 193 seg23 2430 1043 124 dummy 4843 - 980 159 com9 4470 1043 194 seg24 2370 1043 125 com39 4843 - 910 160 com8 4410 1043 195 seg25 2310 1043 126 com38 4843 - 850 161 com7 4350 1043 196 seg26 2250 1043 127 com37 4843 - 790 162 com6 4290 1043 197 seg27 2190 1043 128 com36 4843 - 730 163 com5 4230 1043 198 seg28 2130 1043 129 com35 4843 - 670 164 com4 4170 1043 199 seg29 2070 1043 130 com34 4843 - 610 165 com3 4110 1043 200 seg30 2010 1043 131 com33 4843 - 550 166 com2 4050 1043 201 se g31 1950 1043 132 com32 4843 - 490 167 com1 3990 1043 202 seg32 1890 1043 133 com31 4843 - 430 168 com0 3930 1043 203 seg33 1830 1043 134 com30 4843 - 370 169 coms 3870 1043 204 seg34 1770 1043
s6b0759 81 com/128 seg driver & control ler for stn lcd 8 table 2. pad center coordinates (continued) [unit : m m] pad pad coordinate pad pad coordinate pad pad coordinate no. name x y no. name x y no. name x y 205 seg35 1710 1043 240 seg70 - 390 1043 275 seg105 - 2490 1043 206 seg36 1650 1043 241 seg71 - 450 1043 276 seg106 - 2550 1043 207 seg37 1590 1043 242 seg72 - 510 1043 277 seg107 - 2610 1043 208 seg38 1530 1043 243 seg73 - 570 1043 278 seg108 - 2670 1043 209 seg39 1470 1043 244 seg74 - 630 1043 279 seg109 - 2730 1043 210 seg40 1410 1043 245 seg75 - 690 1043 280 seg110 - 2790 1043 211 seg41 1350 1043 246 seg76 - 750 1043 281 seg111 - 2850 1043 212 seg42 1290 1043 247 seg77 - 810 1043 282 seg112 - 2910 1043 213 seg43 1230 1043 248 seg78 - 870 1043 283 seg113 - 2970 1043 214 seg44 1170 1043 249 seg79 - 930 1043 284 seg114 - 3030 1043 215 seg45 1110 1043 250 seg80 - 990 1043 285 seg115 - 3090 1043 216 seg46 1050 1043 251 seg81 - 1050 1043 286 seg116 - 3150 1043 217 seg47 990 1043 252 seg82 - 1110 1043 287 seg117 - 3210 1043 218 seg48 930 1043 253 seg83 - 1170 1043 288 seg118 - 3270 1043 219 seg49 870 1043 254 seg84 - 1230 1043 28 9 seg119 - 3330 1043 220 seg50 810 1043 255 seg85 - 1290 1043 290 seg120 - 3390 1043 221 seg51 750 1043 256 seg86 - 1350 1043 291 seg121 - 3450 1043 222 seg52 690 1043 257 seg87 - 1410 1043 292 seg122 - 3510 1043 223 seg53 630 1043 258 seg88 - 1470 1043 293 se g123 - 3570 1043 224 seg54 570 1043 259 seg89 - 1530 1043 294 seg124 - 3630 1043 225 seg55 510 1043 260 seg90 - 1590 1043 295 seg125 - 3690 1043 226 seg56 450 1043 261 seg91 - 1650 1043 296 seg126 - 3750 1043 227 seg57 390 1043 262 seg92 - 1710 1043 297 seg127 - 3810 1043 228 seg58 330 1043 263 seg93 - 1770 1043 298 com40 - 3870 1043 229 seg59 270 1043 264 seg94 - 1830 1043 299 com41 - 3930 1043 230 seg60 210 1043 265 seg95 - 1890 1043 300 com42 - 3990 1043 231 seg61 150 1043 266 seg96 - 1950 1043 301 com43 - 4050 1 043 232 seg62 90 1043 267 seg97 - 2010 1043 302 com44 - 4110 1043 233 seg63 30 1043 268 seg98 - 2070 1043 303 com45 - 4170 1043 234 seg64 - 30 1043 269 seg99 - 2130 1043 304 com46 - 4230 1043 235 seg65 - 90 1043 270 seg100 - 2190 1043 305 com47 - 4290 1043 236 seg66 - 150 1043 271 seg101 - 2250 1043 306 com48 - 4350 1043 237 seg67 - 210 1043 272 seg102 - 2310 1043 307 com49 - 4410 1043 238 seg68 - 270 1043 273 seg103 - 2370 1043 308 com50 - 4470 1043 239 seg69 - 330 1043 274 seg104 - 2430 1043 309 com51 - 4530 1043
81 com/128 seg drive r & controller for s tn lcd s6b0759 9 ta ble 2. pad center coordinates (continued) [unit : m m] pad pad coordinate pad pad coordinate pad pad coordinate no. name x y no. name x y no. name x y 310 com52 - 4590 1043 322 com60 - 4843 290 333 com1 - 4843 - 370 311 dummy - 4660 1043 323 com61 - 4843 230 334 com72 - 4843 - 430 312 dummy - 4740 1043 324 com62 - 4843 170 335 com73 - 4843 - 490 313 dummy - 4843 860 325 com63 - 4843 110 336 com74 - 4843 - 550 314 dummy - 4843 780 326 com64 - 4843 50 337 com75 - 4843 - 610 315 com53 - 4843 710 327 com65 - 4843 - 10 338 com76 - 4843 - 670 316 com54 - 4843 650 328 com66 - 4843 - 70 339 com77 - 4843 - 730 317 com55 - 4843 590 329 com67 - 4843 - 130 340 com78 - 4843 - 790 318 com56 - 4843 530 330 com68 - 4843 - 190 341 com79 - 4843 - 850 319 com57 - 4843 470 331 com69 - 4843 - 250 342 coms1 - 4843 - 910 320 com58 - 4843 410 332 com70 - 4843 - 310 343 dummy - 4843 - 980 321 com59 - 4843 350
s6b0759 81 com/128 seg driver & control ler for stn lcd 10 pin description power supply table 3. power supply pins name i/o description v dd supply power supply vss1 vss2 supply ground vss1 and vss2 must be s horted to external wire. v0 v1 v2 v3 v4 i/o lcd driver supplies voltages the voltage determined by lcd pixel is impedance converted by an operational amplifier for application. voltages should have the following relationship; v0 3 v1 3 v2 3 v 3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/n bias (n - 1)/n x v0 (n - 2)/n x v0 (2/n) x v0 (1/n) x v0 note: n = 4 to 11 lcd dri ver supply table 4. lcd driver supply pins name i/o description c1 - o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2 - o capacitor 2 negative connection pin for voltage convert er c2+ o capacitor 2 positive connection pin for voltage converter c3+ o capacitor 3 positive connection pin for voltage converter c4+ o capacitor 4 positive connection pin for voltage converter c5+ o capacitor 5 positive connection pin for voltage con verter vout i/o voltage converter input/output pin vci i voltage converter input voltage pin vr i v0 voltage adjustment pin it is valid only when on - chip resistors are not used (intrs = "l") ref i selects the external vref voltage via vext pin - ref = "l": using the external vref - ref = "h": using the internal vref vext i externally input reference voltage (vref) for the internal voltage regulator it is valid only when ref is "l".
81 com/128 seg drive r & controller for s tn lcd s6b0759 11 system control table 5. system control pins name i/o description in trs i internal resistors select pin. this pin selects the resistors for adjusting v0 voltage level. - intrs = "h": use the internal resistors - intrs = "l": use the external resistors vr pin and external resistive divider control v0 voltage. test1 to test4 i test pins don't use these pins.
s6b0759 81 com/128 seg driver & control ler for stn lcd 12 microprocessor inter face table 6. microprocessor interface pins name i/o description resetb i reset the input pin when resetb is "l", initialization is executed. ps0 i parallel/serial data input select input ps0 interface mode data/ instruction data read/write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs or none sid(db7) write only sclk(db6) note: when ps is "l", db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either "h" or "l". ps1 i microprocessor interface select input pin - ps0 = "h" , ps1 = "h": 6800 - series parallel mpu interface - ps0 = "h" , ps1 = "l": 8080 - series parallel mpu interface - ps0 = "l" , ps1 = "h": 4 pin - spi serial mpu interface - ps0 = "l" , ps1 = "l": 3 pin - spi serial mpu interface cs1b i chip select input pins data/instruction i/o is enabled only when cs1b is "l" . when chip select is non - active, db0 to db7 may be high impedance. rs i register select input pin - r s = "h": db0 to db7 are display data - rs = "l": db0 to db7 are control data rw_wr i read/write execution control pin ps1 mpu type rw_wr description h 6800 - series rw read/write control input pin - rw = "h": read - rw = "l": write l 8080 - series /w r write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal.
81 com/128 seg drive r & controller for s tn lcd s6b0759 13 table 6. microprocessor interface pins (continued) name i/o description e_rd i read/write execution control pin ps1 mpu type e_rd description h 6800 - series e read/write control input pin - rw = "h": when e is "h", db0 to db7 are in an output status. - rw = "l": the data on db0 to db7 are latched at the falling edge of the e signal. l 8080 - series /rd read enable clock input pin when /rd is "l" , db0 to db7 are in an output status. db0 to db7 i/o 8 - bit bi - directional data bus that is connected to the standard 8 - bit microprocessor data bus. when the serial interface selected (ps0 = "l"); - db0 to db5: high impedance - db6: serial input clock ( sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance. test1 to test4 i/o these test pins should be opened.
s6b0759 81 com/128 seg driver & control ler for stn lcd 14 lcd driver outputs table 7. lcd driver outputs pins name i/o description seg0 to seg127 o lc d segment driver outputs the display data and the m signal control the output voltage of segment driver. display data m (internal) segment driver output voltage normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss com0 to com79 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) common driver output voltage h h v ss h l v0 l h v1 l l v4 powe r save mode v ss coms (coms1) o common output for the icons. the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these pins should be opened (floated).
81 com/128 seg drive r & controller for s tn lcd s6b0759 15 functional descripti on microprocessor inter face ch ip select input there are cs1b for chip selection. the s6b0759 can interface with an mpu only when cs1b is "l" . when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel/serial interface s6b0759 has four types of interface with an mpu, which are two serial and two parallel interface. this parallel or serial interface is determined by ps 0 pin as shown in table 8. table 8. parallel/serial interface mode ps0 type cs1b ps1 interface mode h parallel cs1b h 6800 - series mpu mode l 8080 - series mpu mode l serial cs1b h 4 pin - spi mpu mode l 3 pin - spi mpu mode parallel interface (ps0 = " h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by ps1 as shown in table 9. the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 10. table 9. microprocessor selection for parallel interface ps1 cs1b rs e_rd rw_wr db0 to db7 mpu bus h cs1b rs e rw db0 to db7 6800 - series l cs1b rs /rd /wr db0 to db7 8080 - series table 10. parallel data transfer common 6800 - series 8080 - series description rs e_rd (e) rw_wr (rw) e_rd (/ rd) rw_wr (/wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
s6b0759 81 com/128 seg driver & control ler for stn lcd 16 data read status read data write command write cs1b rs rw e db figure 3. 6800 - series mpu interface protocol (ps0="h", ps1="h") cs1b rs /wr /rd db data read status read data write command write figure 4. 8080 - series mpu interface protocol (ps0="h", ps1="l")
81 com/128 seg drive r & controller for s tn lcd s6b0759 17 serial interface (ps0 = "l") when the s6b0759 is active(cs1b="l"), serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8 - bit s hift register and the 3 - bit counter are reset. the display data/command indication may be controlled either via software or the register select(rs) pin, based on the setting of ps1. when the rs pin is used (ps1 = "h"), data is display data when rs is high, and command data when rs is low. when rs is not used (ps1 = "l"), the lcd driver will receive command from mpu by default. if messages on the data pin are data rather than command, mpu should send data direction command(11101000) to control the data direc tion and then one more command to define the number of data bytes will be write. after these two continuous commands are send, the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into db 6 and processed as 8 - bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data. serial mode ps0 ps1 cs1b rs serial - mo de with rs pin l h cs1b used serial - mode with software command l l cs1b not used 4 pin - spi interface (ps0 = "l" , ps1 = "h") cs1b sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 5. 4 - pin spi timing (rs is used)
s6b0759 81 com/128 seg driver & control ler for stn lcd 18 3 pin - spi interface (ps0 = "l", ps1 = "l") to write data to the ddram, send data direction command in 3 - pin spi mode. data is latched at the rising edge of sclk. and the ddram column address pointer will be increased by one automatically. (1) set page and column address. set page address set column address msb set column address lsb (2)set ddc(data direction command) and no. of data bytes. set data direction command ( for spi mode only): set no. of data bytes(ddl) sclk cs1b 829 830 831 0 0 1 7 8 15 23 sid msb data in page lsb ddc no. of data 3 byte(1) 2 byte(2) 128 byte 0 ~ ~ ~ ~ ~ ~ ~ ~ 1 2 : 1 0 1 1 p3 p2 p1 p0 : 0 0 0 1 0 y6 y5 y4 : 0 0 0 0 y3 y2 y1 y0 1 1 1 0 1 0 0 0 : d7 d6 d5 d4 d3 d2 d1 d0 figure 6. 3 - pin spi timing (rs is not used) t his command is used in 3 - pin spi mode only. it will be two continuous commands, the first byte controls the data direction and informs the lcd driver the second byte will be number of data bytes will be write. after these two commands sending out, the foll owing messages will be data. if data is stopped in transmitting, it is not valid data. new data will be transferred serially with most significant bit first. notes: 1. in spite of transmission of data, if cs1b will be disable, state terminates abnormally. next state is initialized. 2. ddl register value "0" "1" , "127" "128". (decimal value) busy flag the busy flag indicates whether the s6b0759 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will ac cept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
81 com/128 seg drive r & controller for s tn lcd s6b0759 19 data transfer the s6b0759 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 7. and when reading data from on - chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 8. this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. th erefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 7. write timing rs /wr /rd db0 to db7 n mpu signals d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n) dummy d(n+2) figure 8. read timing
s6b0759 81 com/128 seg driver & control ler for stn lcd 20 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 81 - row by 128 - column addressable array. each pixel can be selected when the page and column addresses are specified. the 81 rows are divided into 10 pages o f 8 lines and the 11th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 9. the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. db0 db1 db2 db3 db4 display data ram 0 0 0 - - 1 1 0 1 - - 0 0 1 1 - - 0 1 0 0 - - 1 0 0 1 - - 0 com0 com1 com2 com3 com4 lcd display - - - - - - - - - - figure 9. ram - to - lcd data transfer page address circuit this circuit is for providing a page address to display data ram shown in figure 11. it incorporates 4 - bit page address register changed by only the "set page" instruction. page address 10 (db3 and db 1 are "h", db2 and db0 is "l") is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a line address corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on - chip ram as shown in figure 11 & figure 12. it incorporates 7 - bit line address register changed by only the initial display line instruction and 7 - bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the line address for transferring the 128 - bit ram data to the display data latch circuit. h owever, display data of icons are not scrolled because the mpu can not access line address of icons.
81 com/128 seg drive r & controller for s tn lcd s6b0759 21 column address circuit column address circuit has a 7 - bit preset counter that provides column address to the display data ram as shown in figure 11. when set column address msb/lsb instruction is issued, 7 - bit [y6:y0] is updated. and, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. and the column address counter is independ ent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built - in ram after issuing adc select instruction. refer to the following figure 10. column address [y6:y0] seg output seg0 seg1 seg2 seg3 ... ... seg124 seg125 seg126 seg127 00h 01h 02h 03h ... ... 7ch 7dh 7eh 7fh lcd panel display (adc=0) ... ... lcd panel display (adc=1) ... ... display data 1 0 1 0 ... ... 1 1 0 0 figure 10. the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on/off, reverse display on/off and entire displ ay on/off instructions without changing the data in the display data ram.
s6b0759 81 com/128 seg driver & control ler for stn lcd 22 page0 page2 page1 page7 page3 page9 page8 page address db3 db0 db1 db2 data db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 38h 40h 3fh 3eh 3dh 3ch 3bh 3ah 39h 41h 42h 43h 44h 45h 46h 47h 48h 4fh 4eh 4dh 4ch 4bh 4ah 49h com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com63 com62 com61 com60 com59 com57 com58 com56 com31 com64 com73 com72 com71 com70 com69 com67 com68 com66 com65 com74 com77 com76 com75 initial start line address = 00h 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 line address com output com78 com79 com0 - - - - - - - - - - seg127 seg126 seg1 seg0 seg125 seg124 seg123 seg122 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output 7f 7d 7b 7c 7a 00 - 02 04 03 05 05 04 03 01 02 00 7a 7b 7c 7e 7d 7f 01 7e 1/81 duty 1/73 duty inistial line register = 00h page10 db0 coms 1 0 1 0 figure 11. display data ram map (initial line address = 00h)
81 com/128 seg drive r & controller for s tn lcd s6b0759 23 page0 page2 page1 page7 page3 page9 page8 page address db3 db0 db1 db2 data db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 38h 40h 3fh 3eh 3dh 3ch 3bh 3ah 39h 41h 42h 43h 44h 45h 46h 47h 48h 4fh 4eh 4dh 4ch 4bh 4ah 49h com1 com0 com79 com78 com77 com75 com76 com74 com73 com2 com11 com10 com9 com8 com7 com5 com6 com4 com3 com12 com21 com20 com19 com18 com17 com15 com16 com14 com13 com22 com55 com54 com53 com52 com51 com49 com50 com48 com23 com56 com65 com64 com63 com62 com61 com59 com60 com58 com57 com66 com69 com68 com67 initial start line address = 00h 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 line address com output com70 com71 com72 - - - - - - - - - - seg127 seg126 seg1 seg0 seg125 seg124 seg123 seg122 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output 7f 7d 7b 7c 7a 00 - 02 04 03 05 05 04 03 01 02 00 7a 7b 7c 7e 7d 7f 01 7e page10 db0 coms 1 0 1 0 1/73 duty inistial line register = 00h 1/81 duty end = 70h start = 80h figure 12. display data ram map (initial line address = 08h)
s6b0759 81 com/128 seg driver & control ler for stn lcd 24 lcd d isplay circuits oscillator this is completely on - chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit ge nerates some signals to be used for displaying lcd. the display clock, cl(internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on - chip ram is generated in synchro nization with the display clock and the display data latch circuit latches the 128 - bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data r am from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line s ignal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 13.
81 com/128 seg drive r & controller for s tn lcd s6b0759 25 fr(internal) com0 com1 segn 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 1 2 3 4 5 6 cl(internal) v0 v1 v2 v3 v ss v0 v4 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss m(internal) 75 76 77 78 79 80 81 figure 13. 2 - frame ac driving waveform (duty ratio = 1/81) fr(internal) com0 com1 segn 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 3 4 5 6 cl(internal) v0 v1 v2 v3 v ss v0 v4 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss m(internal) 75 76 77 78 79 80 81 1 2 figure 14. n - line inve rsion driving waveform (n = 5 , duty ratio = 1/81)
s6b0759 81 com/128 seg driver & control ler for stn lcd 26 lcd driver circuit 81 - channel common driver and 128 - channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m(internal) signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 m v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 15. segment and common timing
81 com/128 seg drive r & controller for s tn lcd s6b0759 27 partial display on lcd the s6b0759 realizes the partial display function on lcd with low - duty driving for saving power consumption and showing the various display duty. to show the various dis play duty on lcd, lcd driving duty and bias are programmable via the instruction. and, built - in power supply circuits are controlled by the instruction for adjusting the lcd driving voltages -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 16. reference example for parti al display (display duty = 25) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 17. partial display (partial display duty = 17, initial com0 = 0)
s6b0759 81 com/128 seg driver & control ler for stn lcd 28 -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 18. moving display (partial display duty = 17, initial com0 = 8) power supply circuit s the p ower supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low - power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they a re valid only in master operation and controlled by power control instruction. for details, refers to "instruction description". table 11 shows the referenced combinations in using power supply circuits. table 11. recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used. 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used. 0 1 1 off on on external input open open only the voltage follower circuits are used. 0 0 1 off off on open external input open only the external power supply circuits are used. 0 0 0 off off off open external input external input
81 com/128 seg drive r & controller for s tn lcd s6b0759 29 voltage converter circuits t hese circuits boost up the electric potential between vci and v ss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by "set dc - dc step - up" in struction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vout = 3 x vci vout c4+ c2+ c2- c1 c3+ v ss vci v ss c1- c1+ c1 c1 c5+ - + - + - + figure 19. three times boosting circuit vout = 4 x vci vout c4+ c2+ c2- c1 c3+ v ss vci v ss c1- c1+ c1 c1 c1 - + c5+ - + - + - + figure 20. four times boosting circuit vout = 5 x vci vout c4+ c2+ c2- c3+ v ss vci v ss c1- c1+ c1 c1 c1 c1 c1 - + c5+ - + - + - + - + figure 21. five times boosting circuit vout = 5 x vci vout c4+ c2+ c2- c3+ v ss vci v ss c1- c1+ c1 c1 c1 c1 c1 - + c5+ - + - + - + - + - + c1 figure 22. six times boosting circuit
s6b0759 81 com/128 seg driver & control ler for stn lcd 30 voltage regulator circuits the function of the internal voltage regulator circuits is to determine liquid crystal opera ting voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational - amplifier circuits shown in figure , it is necessary to be applied internally or external ly. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "s et reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in ta ble . v0 = (1 + rb ra ) x v ev [v] ------ (eq.1) v ev = (1 - ( 63 - a ) 210 ) x v ref [v] ------ (eq.2) ta ble 12. v ref voltage at ta = 25 c ref temp. coefficient v ref [ v ] 1 - 0.075%/ c 2.1 0 external input vext gnd ra vss v0 vr v ev + - rb vout figure 23. internal voltage regulator circuit
81 com/128 seg drive r & controller for s tn lcd s6b0759 31 in case of using internal resistors, ra and rb (intrs = "h") when intrs p in is "h", resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 13. internal rb/ra ratio depending on 3 - bit da ta (r2 r1 r0) 3 - bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb/ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2 figure 24 shows v0 voltage measured by adjusting internal regulator resistor ratio (rb/ra) and 6 - bit electronic v olume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 electronic volume register (0 to 63) v0 voltage [v] (1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) 63 figure 24. electronic volume level (temp. coefficient = - 0.075%/ c)
s6b0759 81 com/128 seg driver & control ler for stn lcd 32 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is "l", it is necess ary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 ua from eq.1 10 = (1 + rb ra ) x v ev [v] ------ (eq.3) from eq. 2 v ev = (1 - ( 63 - 32 ) 210 ) x 2.1 = 1.79 [v] ------ (eq. 4) from requirement 3. 10 ra + rb = 1 [ua] ------ (eq. 5) from equations eq. 3, 4 and 5 ra = 1.79 [m w ] rb = 8.21 [m w ] table 14 shows the range of v0 depending on the above requirements. table 14. the range of v0 electronic volume level 0 ....... 32 ....... 63 v0 8.21 ....... 10.00 ....... 11.73 voltage follower circuits vlcd voltage ( v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the voltage follower for increasing drive capability. table 15 shows the relationship between v1 to v4 level and each duty ratio. table 15. voltage follower circuit lcd bias v1 v2 v3 v4 remarks 1/n (n - 1)/n x v0 (n - 2)/n x v0 2/n x v0 1/n x v0 n = 4 to 11
81 com/128 seg drive r & controller for s tn lcd s6b0759 33 referece circuit exa mples [c1 = 1.0 to 4.7 [ m f], c2 = 0.47 to 2.0 [ m f]] c2 - c2 - c2 - c2 - c2 - + + + + + c1 c1 c1 c1 ra rb c2 v ss - c2 - c2 - c2 - c2 - when using internal regulator resistors c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 intrs v dd when not using internal regulator resistors v ss c4+ c1 + + + + + c1 c1 v ss c1 c1 c1 v ss 1 v ss 2 c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 intrs c4+ v ss 1 v ss 2 vout c5+ c1 vout c5+ c1 figure 25. when using all lcd power cir cuits (6 - time v/c: on, v/r: on, v/f: on) c2 - c2 - c2 - c2 - c2 - + + + + + ra rb c2 v ss - c2 - c2 - c2 - c2 - when using internal regulator resistors c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 intrs v dd when not using internal regulator resistors v ss c4+ + + + + + intrs v ss 1 v ss 2 external power supply v ss external power supply vout c5+ c3+ c1- c1+ c2+ c2- vr v0 v1 v2 v3 v4 c4+ vout c5+ v ss 1 v ss 2 figure 26. when using some lcd power circuits (v/c: off, v/r: on, v/f: on)
81 com/1 28 seg driver & cont roller for stn lcd s6b0759 34 - + - + - + - + - + c3+ c1- c1+ c2+ c2- vr intrs c4+ v0 v1 v2 v3 v4 v ss v dd external power supply v ss 1 v ss 2 vout c3+ figure 27. when using only voltage follower circuit (v/c: off, v/r: off, v/f: on) c3+ c1- c1+ c2+ c2- vr intrs c4+ v0 v1 v2 v3 v4 v ss v dd external power supply v ss 1 v ss 2 vout c5+ figure 28. when not using all lcd power circuits (v/c: off, v/r: off, v/f: off)
81 com/128 seg drive r & controller for s tn lcd s6b0759 35 reset circuit setting resetb to "l" or reset instruction can initialize internal function. when resetb becomes "l", following procedure is occurred. ? p age address: 0 ? column address: 0 ? modify - read: off ? display on/off: off ? initial display line: 0 (first) ? initial com0 register: 0 (com0) ? partial display duty ratio: 1/80 ? icon enable/disable :0(disable) ? reverse display on/off: off (normal) ? n - line inversion register: 0 (disable) ? entire display on/off: off (normal) ? power control register (vc, vr, vf) = (0, 0, 0) ? dc - dc step up: 3 times converter circuit = (0, 0) ? regulator resistor select register: (r2, r1, r0) = (0, 0, 0) ? reference volt age control register: (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) ? lcd bias ratio: 1/10 ? shl select: off (normal) ? adc select: off (normal) ? oscillator status: off ? power save mode: release when reset instruction is issued, following procedure is occurred. ? page address: 0 ? column address: 0 ? modify - read: off ? initial display line: 0 (first) ? regulator resistor select register: (r2, r1, r0) = (0, 0, 0) ? reference voltage control register (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) ? other instruction registers : not changed while resetb is "l" or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes "l", any instruction can be accepted. resetb must be connec ted to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
s6b0759 81 com/128 seg driver & control ler for stn lcd 36 instruction descript ion table 16. instruction table instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy on res 0 0 0 0 1 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address m sb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset modify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode display on/of f 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on set initial display line register 0 0 0 1 0 0 0 0 2 - byte instruction to specify the initial display line to realize vertical 0 0 s6 s5 s4 s3 s2 s1 s0 scrolling set initial com0 register 0 0 0 1 0 0 0 1 2 - byte instruction to specify the initial com0 to realize window 0 0 c6 c5 c4 c3 c2 c1 c0 scrolling set partial display duty ratio 0 0 0 1 0 0 1 0 2 - byte instruction to set partial 0 0 d6 d5 d4 d3 d2 d1 d0 display duty r atio set n - line inversion 0 0 0 1 0 0 1 1 2 - byte instruction to set n - line 0 0 n4 n3 n2 n 1 n0 inversion register release n - line inversion 0 0 1 1 1 0 0 1 0 0 release n - line inversion mode reverse display on/off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display entire display on/off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on icon enable/disable 0 0 1 0 1 0 0 0 1 icon icon = 0 :icon disable icon = 1 :icon enable note: " " is don't care.
81 com/128 seg drive r & controller for s tn lcd s6b0759 37 t able 16. instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc - dc step - up 0 0 0 1 1 0 0 1 dc1 dc0 select the step - up of the internal volt age converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor set electronic volume 0 0 1 0 0 0 0 0 0 1 2 - byte instruction to specify the register 0 0 ev5 ev4 ev3 ev2 ev1 ev0 electronic v olume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl select 0 0 1 1 0 0 shl com bi - directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi - directional selection adc = 0: normal direction adc = 1: reverse direction set data direction & display 1 1 1 0 1 0 0 0 2 - byte instruction to specify the data length(ddl) d7 d6 d5 d4 d3 d2 d1 d0 number of data bytes(spi mode). oscillator on start 0 0 1 0 1 0 1 0 1 1 st art the built - in oscillator set power save mode 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction. note: " " is don't care.
s6b0759 81 com/128 seg driver & control ler for stn lcd 38 read display data 8 - bit data from display data ram specified by the column address and page address can be read by this instruction. as the col umn address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be rea d through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8 - bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column add ress is incremented by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write continue ? data write set column address set page address optional status column = column + 1 no yes figure 29. sequence for writing display data dummy data read set column address set page address optional status column = column + 1 no yes data read column = column + 1 data read continue ? figure 30. sequence for reading display data
81 com/128 seg drive r & controller for s tn lcd s6b0759 39 read status indicates the internal status of the s6b0759 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy on res 0 0 0 0 1 flag description busy the device is busy when internal operat ion or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. on indicates display on/off status. 0: display on, 1: display off res indicates the initialization is in progress by resetb signal. 0: chip is activ e, 1: chip is being reset. set page address sets the page address of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column a ddress, the page address defines the address of the display ram to write or read display data. changing the page address doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 selected page descr iption 0 0 0 0 0 accessible pages for displaying 0 0 0 1 1 dot - matrix display data. 0 0 1 0 2 : : : : : 1 0 0 1 9 1 0 1 0 10 accessible page for displaying icons 1 0 1 1 11 not accessible page. 1 1 0 0 12 do not use these pages. 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15
s6b0759 81 com/128 seg driver & control ler for stn lcd 40 set column address sets the column address of display ram from the microprocessor into the column address register. along with the page address, the column address defines the address of the display ram to write or read display da ta. when the microprocessor reads or writes display data to or from display ram, column addresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127
81 com/128 seg drive r & controller for s tn lcd s6b0759 41 set modify - read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify - read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify - read this instruction cancels the modify - read mode, and makes the column address return to its initial value just before the set modify - read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 change complete? set modify-read reset modify-read set page address data process no yes set column address (n) dummy read data read data write return column address (n) figure 31. sequence for cursor display
s6b0759 81 com/128 seg driver & control ler for stn lcd 42 display on /off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2 - byte in struction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 0 0 1 1 1 0 78 1 0 0 1 1 1 1 79 1 0 1 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation setting initial display line start 1 st instruction (2-byte instruction for mode setting) 2 nd instruction (2-byte instruction for register setting) setting iinitial display line end figure 32. the sequence for setting the i nitial display line
81 com/128 seg drive r & controller for s tn lcd s6b0759 43 set initial com0 register sets the initial row (com0) of the lcd panel using the 2 - byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 0 0 0 0 0 1 1 com3 : : : : : : : : 1 0 0 1 1 0 0 com76 1 0 0 1 1 0 1 com77 1 0 0 1 1 1 0 com78 1 0 0 1 1 1 1 com79 1 0 1 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation setting initial com0 start 1 st instruction (mode setting) 2 nd instruction (initial com0 setting) setting iinitial com0 end figure 33. sequence for setting the initial com0
s6b0759 81 com/128 seg driver & control ler for stn lcd 44 set par tial display duty ratio sets the duty ratio within range of 17 to 81 to realize partial display by using the 2 - byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d6 d5 d4 d3 d2 d1 d0 icon enable/disable bit = 0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 0 1 1 1 1 no operation 0 0 1 0 0 0 0 1/16 0 0 1 0 0 0 1 1/17 0 0 1 0 0 1 0 1/18 0 0 1 0 0 1 1 1/19 : : : : : : : : 1 0 0 1 1 0 1 1/77 1 0 0 1 1 1 0 1/78 1 0 0 1 1 1 1 1/79 1 0 1 0 0 0 0 1/80 1 0 1 0 0 0 1 : : : : : : : 1 1 1 1 1 1 1 no operation
81 com/128 seg drive r & controller for s tn lcd s6b0759 45 icon enable/disable bit = 1 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 1 0 0 0 0 no operation 0 0 1 0 0 0 1 1/17 0 0 1 0 0 1 0 1/18 0 0 1 0 0 1 1 1/19 0 0 1 0 1 0 0 1/20 : : : : : : : : 1 0 0 1 1 1 0 1/78 1 0 0 1 1 1 1 1/79 1 0 1 0 0 0 0 1/80 1 0 1 0 0 0 1 1/81 1 0 1 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation setting partial display start 1 st instruction (mode setting) 2 nd instruction (partial display duty setting) setting partial display end figure 34. sequence for setting partial display
s6b0759 81 com/128 seg driver & control ler for stn lcd 46 set n - line inversion register sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the ph ase of the internal lcd ac signal (internal m) by using the 2 - byte instruction. the dc bias problem could be occurred if k is even number. so, we recommend customers to set k to be odd number. k:d/n d: the number of display duty ratio(d is selectable b y customers) n: n for n - line inversion(n is selectable by customers). the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n - line inversion 0 0 0 0 0 0 - line inversion (frame inversion) 0 0 0 0 1 3 - line inversion 0 0 0 1 0 4 - line inversion : : : : : : 1 1 1 0 1 31 - line inversion 1 1 1 1 0 32 - line inversion 1 1 1 1 1 33 - line inver sion setting n-line inversion start 1 st instruction (mode setting) 2 nd instruction (n-line inversion setting) setting n-line inversion end figure 35. sequence for setting partial display
81 com/128 seg drive r & controller for s tn lcd s6b0759 47 release n - line inversion returns to the frame inversion condition from the n - line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0 reverse di splay on/off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = "1" ram bit data = "0" 0 (normal) lcd pixel is illuminated. lc d pixel is not illuminated. 1 (reverse) lcd pixel is not illuminated. lcd pixel is illuminated. entire display on/off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the displ ay data ram are held. this instruction has priority over the reverse display on/off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = "1" ram bit data = "0" 0 (normal) lcd pixel is illuminated. lcd pixel is not illuminated. 1 (entire) lcd pixel is illuminated. lcd pixel is illuminated. icon enable/disable allows the icon driver circuit to be enabled or disabled, thus changing the duty ratio setting. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 ic on i duty ratio range 0 (disable) 1/16 to 1/80 1 (enable ) 1/17 to 1/81
s6b0759 81 com/128 seg driver & control ler for stn lcd 48 power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal power supply functions can be used simultaneousl y. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off. internal voltage converter circuit is on. 0 1 internal voltage regulator circuit is of f. internal voltage regulator circuit is on. 0 1 internal voltage follower circuit is off. internal voltage follower circuit is on. select dc - dc step - up selects one of 4 dc - dc step - up to reduce the power consumption by this instruction. it is very use ful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc - dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times b oosting circuit regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to table . rs rw db7 db6 db5 db4 db 3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb/ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
81 com/128 seg drive r & controller for s tn lcd s6b0759 49 set electronic volume register consists of 2 - byte instruction the 1 st instruction sets electronic volume mode, the 2 nd one updates the con tents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 e v3 ev2 ev1 ev0 ev5 ev4 ev3 ev2 ev1 ev0 reference voltage ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 setting electronic volume start 1 st instruction for mode setting 2 nd instruction for register setting setting electronic volume end figure 36. sequence for setting the electronic volume
s6b0759 81 com/128 seg driver & control ler for stn lcd 50 select lcd bias sel ects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/10 1 1 1 1/11 shl sel ect com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com79) shl = 1: reverse direction (com79 ? com0 ) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins could be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg127) adc = 1: reverse direction (seg127 ? seg0)
81 com/128 seg drive r & controller for s tn lcd s6b0759 51 set data direction & display data length (3 - pin spi mode) consists of two bytes instruction. this command is used in 3 - pin spi mode only(ps0 = "l" a nd ps1 = "l"). it will be two continuous commands, the first byte control the data direction(write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction i s used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 1 1 0 1 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 oscillator on start this instruction enables the built - in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply, which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
s6b0759 81 com/128 seg driver & control ler for stn lcd 52 power save the s6b0759 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instruc tions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 set power save mode release power save mode sleep mode oscillator circuits: off lcd power supply circuits: off all com / seg output level: v ss release sleep mode figure 37. power save routine nop non operation instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
81 com/128 seg drive r & controller for s tn lcd s6b0759 53 referential instruc tion setup flow: initializing with the built - in power supply circuits end of initialization waiting for stabilizing the lcd power levels set the lcd operating voltage by internal instructions [oscillator on start] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] start of initialization resetb pin = "h" waiting for stabilizing the power power on (v dd -v ss ) with keeping the resetb pin = "l" user system setup by external pins turn on the voltage follower by internal instructions [power control: vc=1, vr=1, vf=1] turn on the voltage regulator by internal instructions [power control: vc=1, vr=1, vf=0] turn on the voltage converter by internal instructions [power control: vc=1, vr=0, vf=0] wating for 50% rising of vout wating for 3 1ms figure 38. initializing with the built - in power supply circuits
s6b0759 81 com/128 seg driver & control ler for stn lcd 54 referential instruction setup flow: initializing without the built - in power supply circuits user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] set the lcd operating voltage by internal instructions [oscillator on] [regulator or flower register select] [power control] resetb pin = "h" set power save release power save power on (v dd -v ss ) with keeping the resetb pin = "l" user system setup by external pins start of initialization waiting for stabilizing the power waiting for stabilizing the lcd power levels end of initialization figure 39. initializing without the built - in power supply circuits
81 com/128 seg drive r & controller for s tn lcd s6b0759 55 referential instruction setup flow: data displaying end of initialization write initial display data by instruction [display data write] turn display on by instruction [display on/off: d=1] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 40. data displaying referential instruction setup flow: power off optional status power off (v dd -v ss ) end of power off set power save by instruction figure 41. power off
s6b0759 81 com/128 seg driver & control ler for stn lcd 56 referential instruction setup flow: partial duty changing waiting for discharging the lcd power levels start of partial changing set display off by internal [display on / off: d=0] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] set the lcd operating voltage for partial display by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select [lcd bias register select] waiting for stabilizing the lcd power levels end of partial changing release power save set sleep mode by internal instruction set [power save mode] write display data & display on by internal instruction [display data write] [display on / off: d=1] figure 42. partial duty changing note : partial com0 register setting for com h/w half: [80 ? (user duty)]/2
81 com/128 seg drive r & controller for s tn lcd s6b0759 57 specifications absolute maxi mum ratings table 17. absolute maximum ratings (v ss = 0v) parameter symbol rating unit supply voltage range v dd - 0.3 to + 7.0 v v 0 , v out - 0.3 to + 17.0 v v 1 , v 2 , v 3 , v 4 - 0.3 to v 0 + 0.3 v external reference voltage v ext + 0.3 to v dd v input vo ltage range v in - 0.3 to v dd + 0.3 v operating temperature range t opr - 40 to + 85 c storage temperature range t str - 55 to + 125 c notes: 1. v dd , v0, vout, v1 to v4, vext and vci are based on v ss = 0v. 2. voltage vout 3 v0 3 v1 3 v2 3 v3 3 v4 3 v ss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi m ay malfunction or reduced lsi reliability may result.
s6b0759 81 com/128 seg driver & control ler for stn lcd 58 dc characteristics table 18. dc characteristics (v ss = 0v, v dd = 1.8 to 3.3v, ta= - 40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 1.8 - 3.3 v v dd (1) operating voltage (2) v 0 4.0 - 15.0 v v 0 (2) input voltage high v ih 0.8v dd - v dd low v il v ss - 0.2v dd v (3) output high v oh i oh = - 0.5ma 0.8v dd - v dd voltage low v ol i ol = 0.5ma v ss - 0.2v dd v (4) input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a (3) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a (5) lcd driver on resistance r on ta = 25 c, v 0 = 8v - 2.0 3.0 k w segn comn (6) frame frequency f fr ta = 25 c 70 85 100 hz (7) voltage converter vci x 3 1.8 - 3.6 input voltage x 4 1.8 - 3.6 x 5 1.8 - 3.0 x 6 1.8 - 2.5 v vci voltage converter circuit output voltage v out 3/ 4/ 5/ 6 voltage conversion (no - load ) 95 99 - % v out voltage regulator circuit operating voltage v out 5.4 - 15.0 v v out voltage fol lower circuit operating voltage v 0 4.0 - 15.0 v v 0 (8) reference voltage v ref ta = 25 c 2.04 2.10 2.16 v (9)
81 com/128 seg drive r & controller for s tn lcd s6b0759 59 dynamic current consumption (1) when an external power supply is used. table 19. dynamic current 1 (external power) (v dd = 2.4v, ta = 25 c) item symbol condition min typ max unit pin used v 0 - v ss 12.0v, duty = 1/81 (display off) - 7.5 10 m a (10) dynamic current consumption (1) i dd1 v 0 - v ss 12.0v, duty = 1/81 (display on , checker pattern) - 10 15 m a (10) dynamic current consumption (2) whe n the internal power supply is on table 20. dynamic current 2 (internal power) (v dd = 2.4v, ta = 25 c) item symbol condition min. typ. max. unit pin used v 0 - v ss 12.0v, x5 boosting, duty = 1/81, normal mode (display off) - 120 190 m a (10) dynamic current consumption (2) i dd2 v 0 - v ss 12.0v, x5 boosting, duty = 1/81, normal mode (display on , checker pattern) - 210 300 m a (10) current consumption during power save mode table 21. power save mode current (v dd = 2.4v, ta = 25 c) item symbol condition m in. typ. max. unit pin used sleep mode current i dds1 during sleep - - 3 m a (10)
s6b0759 81 com/128 seg driver & control ler for stn lcd 60 table 22. the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on - chip oscillator circuit is used f fr x n f fr x 4 x n (f o sc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 17 to 81) notes: 1. though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. 2. in case of external power supply is applied. 3. cs1b, rs, db0 to db7, e_rd, rw_wr, resetb, ps1, ps0, intrs, and ref. 4. db0 to db7 5. applies when the db0 to db7 pins are in high impedance. 6. resistance value when - 0.1[ma] is applied during the on st atus of the output pin segn or comn. ron [k w ] = d v[v]/0.1[ma] ( d v : voltage change when - 0.1[ma] is applied in the on status.) 7. see table for the relationship between oscillation frequency and frame frequency. 8. the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. 9. on - chip reference voltage source of the voltage regulator circuit to adjust v0. 10. applies to the case where the on - chip oscillation circuit is used an d no access is made from the mpu. the current consumption, when the built - in power supply circuit is on or off. the current flowing through voltage regulation resistors(rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
81 com/128 seg drive r & controller for s tn lcd s6b0759 61 ac characteristics read/write characteristics (8080 - series mp) db0 to db7 (write) (read) t dh80 t od80 t ds80 t acc80 t pwlw, t pwlr t cy80 t ah80 t as80 /rd, /wr cs1b rs db0 to db7 0.9v dd 0.1v dd t pwhw, t pwhr figure 43. read/write characteristics (8080 - series mpu) (v dd = 1.8 to 3.3v, ta = - 40 to +85 c) item signal symbol condi tion min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time t cy80 1000 - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw 120 120 - - ns pulse width low for read pulse width hi gh for read e_rd (/rd) t pwlr t pwhr 240 120 - - ns data setup time data hold time db0 to db7 t ds80 t dh80 80 30 - - ns read access time output disable time t acc80 t od80 cl = 100 pf - 10 280 200 ns note: the input signal rise time and fall time (t r , t f ) is specified at 15 ns or less. or (t r + t f ) < (t cy80 - t pwlw - t pwhw ) for write, (t r + t f ) < (t cy80 - t pwlr - t pwhr ) for read.
s6b0759 81 com/128 seg driver & control ler for stn lcd 62 read/write characteristics (6800 - series microprocessor) db0 to db7 resetb /wr /rd rs csb 8080-series mpu csb rs e_rd rw_wr db0 to db7 resetb ps0 ps1 s6b0755 v ss v dd figure 44. read/write characte ristics (6800 - series microprocessor) (v dd = 1.8 to 3.3v, ta = - 40 to +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time t cy68 500 - ns enable width high for write ena ble width low for write e_rd (e) t ewhw t ewlw 60 60 - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr 120 60 - - ns data setup time data hold time t ds68 t dh68 30 5 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - 10 60 50 ns note: the input signal rise time and fall time (t r , t f ) is specified at 15 ns or less. or (t r + t f ) < (t cy80 - t ewhw - t ewlw ) for write, (t r + t f ) < (t cy80 - t ewhr - t ewlr ) for read.
81 com/128 seg drive r & controller for s tn lcd s6b0759 63 serial interface characteristics db6 (sclk) rs cs1b db7 (sid) 0.9v dd 0.1v dd t chs t ahs t ass t cys t wls t css t whs t dss t dhs figure 45. serial interface characteristics (v dd = 1.8 to 2.6v, ta = - 40 to +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t scy t shw t s lw 111 60 60 - - - ns address setup time address hold time rs t ass t ahs 60 60 - - ns data setup time data hold time db7 (sid) t dss t dhs 60 60 - - ns cs1b setup time cs1b hold time cs1b t css t chs 60 60 - - ns (v dd = 2.6v to 3.3v, ta = - 40 to +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t scy t shw t slw 58.8 30 30 - - ns address setup time address hold time rs t ass t ahs 30 30 - - ns data setup time data hold time db7 ( sid) t dss t dhs 30 30 - - ns cs1b setup time cs1b hold time cs1b t css t chs 30 30 - - ns note: the input signal rise time and fall time (t r , t f ) is specified at 15 ns or less.
s6b0759 81 com/128 seg driver & control ler for stn lcd 64 reset input timing resetb internal status t rw during reset reset complete t r figure 46. reset input timing (v dd = 1.8 to 3.3v, ta = - 40 to +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1000 - ns reset time - t r - 1000 ns
81 com/128 seg drive r & controller for s tn lcd s6b0759 65 reference applicatio ns microprocessor inter face in case of interfacing with 6800 - series (ps0 = "h ", ps1 = "h") db0 to db7 resetb rw e rs cs1b 6800-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 s6b0759 v dd v dd figure 47. interfacing with 6800 - series in case of interfacing with 8080 - series (ps0 = "h" , ps1 = "l" ) db0 to db7 resetb /wr /rd rs cs1b 8080-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 s6b0759 v ss v dd figure 48. interfacing with 8080 - series
s6b0759 81 com/128 seg driver & control ler for stn lcd 66 in case of serial peripheral interface wi th rs pin (ps0 = "l" , ps1 = "h" ) resetb sclk sid rs cs1b mpu cs1b rs db7(sid) db6(sclk) ps0 ps1 s6b0759 v ss v dd open db0 to db5 resetb figure 49. 4 - pin serial interface in case of serial peripheral interface with software command (ps0 = "l" , ps1 = "l" ) resetb sclk sid cs1b mpu cs1b rs db7(sid) db6(sclk) ps0 ps1 s6b0759 v ss v ss open db0 to db5 resetb v ss /v dd figure 50. 3 - pin serial interface
81 com/128 seg drive r & controller for s tn lcd s6b0759 67 connections between s6b0759 and lcd panel single chip configurations (1/81 duty) ? a x a ? a x a 80 x 128 pixels com39 com0 coms coms com79 com40 seg127 s6b0759 (bottom view) seg0 seg126 seg1 figure 51. shl = 0, adc = 1 80 x 128 pixels com39 com0 coms coms com79 com40 seg0 s6b0759 (top view) ? a x a ? a x a seg1 seg127 seg126 figure 52. shl = 0, adc = 0 80 x 128 pixels s6b0759 (bottom view) com39 com0 coms coms com79 com40 seg0 ? a x a ? a x a seg1 seg127 seg126 figure 53. s hl = 1, adc = 0 80 x 128 pixels s6b0759 (top view) com39 com0 coms coms com79 com40 seg127 ? a x a ? a x a seg126 seg0 seg1 figure 54. shl = 1, adc = 1

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